1. Field of the Invention
This invention relates generally to data transmission systems, and more particularly to an asynchronous interface for allowing speed-regulated data transmission between two synchronous systems in different clock domains.
2. Description of the Prior Art
Connections of input/output (I/O) systems and central computing complexes (including processing units and memory devices) have often required the use of asynchronous interfaces. It is known that various I/O devices and systems are designed to be used in conjunction with these central computing complexes, however the I/O devices are typically independently designed, and operate at different system clock speeds than the central computing complex. The different system clock speeds of the I/O and the central computing complex have given rise to the use of the asynchronous interface, to allow these synchronous circuits to communicate effectively.
One asynchronous interface method is to use memory buffers in both the I/O system and the central computing complex. These memory buffers temporarily stored additional data transfer requests while waiting for current operations to be completed. Other memory buffers temporarily stored transmitted data which could not yet be handled by the recipient circuit. However, use of these buffers requires complex address counters and pointers, detectors for detecting whether the buffer is empty or full, and queue compression logic. Furthermore, these buffers require large amounts of valuable real estate on the chip. It is therefore desirable to provide an interface between the input/output devices and the memory without the use of the large amount of memory buffers.
U.S. Pat. No. 5,191,657, issued to Ludwig et al. on Mar. 2, 1993, discloses an asynchronous bus interface interposed between independent synchronous buses. However, Ludwig et al. does not appear to provide for an asynchronous interface which can delay the transfer of data depending on the relative speeds of the different synchronous systems. The present invention allows this delay to be easily modified according to changing relative clock rates of the synchronous systems. This provides for ease in coupling a particular I/O system to various different memory systems, and further provides for a modifiable asynchronous interface that is greatly beneficial during clock margin testing.
There is a need, therefore, for an asynchronous bus interface that provides flexibility in changing data transfer rates between two systems clocked at different clock rates, and further for an asynchronous bus interface that avoids the need for large amounts of memory buffers which consume valuable chip real estate. The present invention provides a solution to these and other problems, and offers other advantages over the prior art.